1. Field of the Invention
The present invention relates to an analog-to-digital modulator, especially to a bandwidth tunable sigma-delta ADC modulator.
2. Description of the Prior Art
The analog-to-digital converter (ADC) has been gradually moving toward front end in modern wireless communication receivers to exchange analog selectivity with digital process FIG. 1 shows conventional receiver architecture; the received signal is processed by the SAW filter 110, low-noise amplified by the LNA 120, and then mixed down by the mixer 130. Channel selection filter 140 and programmable gain amplifier (PGA) 150 follow to filter out-of-band interferers and adjust the in-band signal strength. The signal is then converted to digital domain by the ADC 160 for baseband demodulation performed by the digital demodulator 170. There involve several analog-processing stages those introduce process variation and offset. Extra supporting circuitry is needed for calibration and controlling signal strength; it therefore increases the system complexity, risk, and time-to-market.
FIG. 2 demonstrates digitized receiver architecture by moving ADC 160 toward the antenna. Signal processing such as scaling and filtering is combined with signal demodulation in digital domain, and these functions are performed by the digital processor 180, thereby obtaining system optimization, stability and even programmability for multi-standard operation. The burden of this approach falls on the ADC 160 that has to possess high linearity, dynamic range, bandwidth, and low power consumption.
A continuous-time (CT) sigma-delta modulator (ΣΔM) ADC is well suitable for this application for its low power consumption and insensitive to process variation. A discrete-time (switched-capacitor, SC) ΣΔM ADC is popular for its accurate loop filter coefficient control by good capacitor matching. Nevertheless, the SC ΣΔM needs an anti-alias filter before the signal sampled by the loop filter. In addition, the bandwidth of the filter opamp's has to be several times of the sampling frequency and therefore consuming lots of power. A CT ΣΔM with feedforward weighting amplifiers, on the other hand, has the sampling happened at the end of the loop filter; the loop filter itself additionally serves as an anti-alias filter. Moreover, only the first stage of the loop filter needs larger bandwidth and high gain while the rest stages error are suppressed by the first stage. Therefore, a low power ΣΔM ADC is achievable.
Please refer to FIG. 3. FIG. 3 shows a CT ΣΔM ADC with feedforward weighting amplifiers. The CT ΣΔM ADC 300 includes an adder 310, a loop filter 320, a quantizer 340, and a DAC 350. The loop filter 320 includes a plurality n of transconductors, including the first stage transconductor 322 and other stage transconductors 324, and an adder 328. Each transconductor is coupled to a corresponding feedforward weighting amplifier 326. The input terminal of the feedforward weighting amplifier 326 is coupled to the output of the corresponding transconductor, and the output terminal of the feedforward weighting amplifier 326 is coupled to the adder 328. The single-loop structure shown in FIG. 3 is adopted for its simple stability and easy bandwidth modification. The analog input signal is represented by X and the digital output signal is denoted by Y. The quantizer 340 can be implemented by a one-bit quantizer used for better linearity. The quantizer 340 is modeled as a gain stage 342 (gain=k) plus additive noise (N) through an adder 344. The quantizer gain k, changing dynamically, is related to X.
The loop filter of the ΣΔM will be realized by Gm-C structure; the individual unit gain bandwidth is annotated as W1˜Wn with feedforward coefficient a1˜an. The DAC 350 is connected between the output Y and the adder 310 for providing a feedback signal to the input signal X.
There exists stability issue for a ΣΔM design. The stability problem for this single-loop structure is released because once the internal signal becomes large, the later loop filter stage (nth, then (n−1)th and then (n−2)th) will saturate sequentially and provide no AC gain to the quantizer 340. The system will reduce to a 2nd order ΣΔM temporarily and maintain its stability. In addition, it is advisory to shape the noise spectrum as smooth as possible to reduce high frequency disturbance for stability enhancement; a good choice is to design the noise-transfer-function (NTF) as a high-pass Butterworth filter. The loop filter transfer function can be derived as
                                          B            ⁡                          (              S              )                                                          A              ⁡                              (                S                )                                      ⁢                                                                =                                                                              k                  (                                                                                    a                        1                                            ⁢                                              W                        1                                            ⁢                                              S                                                  n                          -                          1                                                                                      +                                                                  a                        2                                            ⁢                                              W                        1                                            ⁢                                              W                        2                                            ⁢                                              S                                                  n                          -                          2                                                                                      +                    …                    +                                                                                                                                                                                          a                                                  n                          -                          1                                                                    ⁡                                              (                                                                                                            W                              1                                                        ·                                                          W                              2                                                                                ⁢                                                                                                          ⁢                          …                          ⁢                                                                                                          ⁢                                                                                    W                                                              n                                -                                2                                                                                      ·                                                          W                                                              n                                -                                1                                                                                                                                    )                                                              ⁢                    S                                    +                                                                                                                          a                    n                                    ⁡                                      (                                                                                            W                          1                                                ·                                                  W                          2                                                                    ⁢                                                                        a                                                      n                            -                            1                                                                          ⁡                                                  (                                                                                                                    W                                1                                                            ·                                                              W                                2                                                                                      ⁢                            …                            ⁢                                                                                                                  ⁢                                                                                          W                                                                  n                                  -                                  1                                                                                            ·                                                              W                                n                                                                                                              )                                                                                      )                                                                                            S            n                                              (        1        )            The STE (signal-transfer-function) and NTF of the system can then be represented as
                              STF          ⁢                      :                      ⁢                                    Y              ⁡                              (                S                )                                                    X              ⁡                              (                S                )                                                    =                              B            ⁡                          (              S              )                                                          A              ⁡                              (                S                )                                      +                          B              ⁡                              (                S                )                                                                        (        2        )                                          NTF          ⁢                      :                      ⁢                                    Y              ⁡                              (                S                )                                                    N              ⁡                              (                S                )                                                    =                              A            ⁡                          (              S              )                                                          A              ⁡                              (                S                )                                      +                          B              ⁡                              (                S                )                                                                        (3)            
The unit-gain bandwidth W1˜Wn are chosen depending on application but W2˜Wn can be smaller than W1 because the later stage errors are all suppressed by the first stage. For simplicity, a five-stage loop filter ADC is taken as an example to explain the poles and zeros. For initial guess and discussion purpose, the quantizer gain k is assumed to be 1. By placing the NTF poles on the left-hand plane Butterworth positions, FIG. 4 demonstrates the NTF pole and zero locations in S-plane, and FIG. 5 shows the corresponding frequency response.
The quantizer gain k, however, changes dynamically. Once the system unit gain bandwidth and feedforward coefficients of the feedforward weighting amplifiers are decided, the variation of k may cause the stability issue to the system FIG. 6 demonstrates the NTF pole movement while k increases from 1, and FIG. 7 demonstrates the NTF pole movement while k decreases from 1. Note that the k change has no affect on the zeros and the NTF poles are also STF poles as mentioned in (2) and (3).
For a large k, the NTF can be approximated as A(S)/B(S); in FIG. 6, four NTF poles approach the zeros of STF and one goes to −∞ on real axis and causes no stability issue. On the other hand, while k decreases from 1, some poles may go to right hand plane (k<kcrit, which is 0.48 here as an exemplary example) and cause system unstable. Fortunately, the decrease of k happens at the situation of large internal signal; the later stages of the loop filter will be saturated (or limited by the natural of the circuit property, e.g., clamped by the power supply) sequentially. The overall loop filter stage is effectively reduced such that the stability range extends.